Semiconductor devices such as Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET's) formed on strained silicon channels have been shown to offer dramatic improvements in mobility and performance. The successful integration of high-performance strained silicon logic type MOSFET's with memory such as dense, low-leakage Dynamic Random Access Memory (DRAM) arrays on the same semiconductor chip for embedded-DRAM applications has not been achieved due to the need to maintain high quality, defect-free silicon in the DRAM array areas while providing strained silicon in the logic support areas. Strained silicon and the substrate required to produce the strain inherently results in greatly increased silicon dislocations, which makes it incompatible with low-leakage DRAM cells. Furthermore, semiconductor processes which exceed certain temperatures that are required for the DRAM cell formation may be incompatible with currently practiced strained silicon formation.
Forming high-performance strained silicon support MOSFETs on the same substrate with low-leakage high-density DRAM cells is desired.